module RegFile(RegWr,Clear,Rw,Ra,Rb,busW,busA,busB,clock);
parameter T_rd = 10, T_wr = 10; 
parameter NRegisters = 32;
parameter RegSize = 32;
parameter AdrSize = 5;

input RegWr,clock, Clear;
input [RegSize-1:0] busW;
input [AdrSize-1:0] Rw,Ra,Rb;
output [RegSize-1:0] busA,busB;
reg [RegSize-1:0] busA,busB;

reg [RegSize-1:0] RegNbit[0:NRegisters-1];

reg[31:0] RegFile[31:0];
reg[5:0] i;


always@(Ra or Rb or Clear)
begin
  if(Clear==0)
    for(i=0; i<32; i = i+1)
       RegFile[i] =0;
  else
    begin
      #T_rd assign busA=RegFile[Ra];
      #T_rd assign busB=RegFile[Rb];
    end
end

always@(posedge clock)
	begin
	if(!Clear)
  	for(i=0; i<32; i = i+1)
      RegFile[i] = 0;
	//write to the register at location Rw
	if(RegWr)
    begin
	     RegFile[Rw] = #T_wr busW;
       RegFile[0] = 0;
    end
	end

endmodule

/*
module TestReg;

   reg  RegWr, clear;
   reg[4:0] Rw, Ra, Rb;
   reg[31:0] busW;
   wire[31:0]        busA, busB;
   wire clock;
      
   m555 clk(clock);
   
   RegFile myreg(RegWr,clear,Rw,Ra,Rb,busW,busA,busB,clock);
   
     
   initial begin
	$monitor($time,"RegWr=%d,Clear=%d,Rw=%d,Ra=%d,Rb=%d,busW=%d,busA=%d,busB=%d,clock=%d", RegWr,clear,Rw,Ra,Rb,busW,busA,busB,clock);  
     	 clear =0; 
	 RegWr=0;
	 Rw=0;
	 Ra=0;
	 Rb=0;
	 busW =0;
	 #5 clear =1;
       #105
	 RegWr=1;
	 Rw=6;
	 Ra=0;
	 Rb=0;
	 busW =4000;
       #100
       RegWr=0;
	 #100
	 RegWr=0;
	 Rw=22;
	 busW =565665;
	 #100
	 RegWr=0;
	 Rw=0;
	 Ra=6;
	 Rb=22;
	 busW =0;
       #100 $finish;
   end
endmodule

*/
